The invention is in the field of multi-level ECL circuitry in which plural gating levels are connected in series between a circuit voltage node and a circuit current source. More particularly, the invention concerns the stabilization of the circuit current magnitude by the regulation of a bias voltage which is fed to the transistor which generates the circuit current.
Both the field of the invention and the limitations of the state of the art in the invention field can be understood with reference to FIG. 1, which is representative of a multi-level ECL gating circuit. The circuit of FIG. 1 is intended to be connected in series with other multi-level gating circuits to implement desired logic functions. The multi-level gating circuit of FIG. 1 includes three gating levels, each responsive to a respective one of three input signals A, B, or C. The first level, responsive to input A, consists of eight transistors, Q.sub.1 -Q.sub.8, which are connected into four emitter-coupled pairs. In this regard, the transistor pair Q.sub.1 and Q.sub.2 are said to be emitter-coupled by virtue of their emitters being connected directly together and their collectors being connected through respective resistors to a common voltage node, in this case, the circuit voltage source node Vcc. A stabilized bias voltage VT.sub.2 is connected to the base of Q.sub.2, while the base of Q.sub.1 receives the input logic signal A. Thus connected, the emitter-coupled pair Q.sub.1 and Q.sub.2 will switch a circuit current according to the magnitude of the signal A with respect to the bias level VT.sub.2. When A exceeds the bias voltage level, Q.sub.1 will be switched on to conduct the circuit current through R.sub.1. When the magnitude of A is less than the level of the threshold voltage at the base of Q.sub.2, the current is switched through Q.sub.2. Thus, the emitter-coupled pair Q.sub.1 and Q.sub.2 form a basic binary circuit which assumes one of two states according to the state of the input signal A.
The first level of the circuit of FIG. 1 includes the four emitter-coupled pairs, Q.sub.1 Q.sub.2, Q.sub.3 Q.sub.4, Q.sub.5 Q.sub.6, and Q.sub.7 Q.sub.8, each of which operates binarily in response to the signal level at the node A. The second gating level responds to the signal at the signal node B, and consists of the two emitter-coupled transistor pairs Q.sub.10 Q.sub.11 and Q.sub.12 Q.sub.13. Each transistor of each second gating level pair is connected in emitter-coupled form, with the collector of each transistor of the pair connected to the coupled emitters of a respective one of the first level transistor pairs. Thus, the collector of the transistor Q.sub.10 in the pair Q.sub.10 Q.sub.11 is connected to the commonly-coupled emitters of the pair Q.sub.1 Q.sub.2 in the first gating level. Each of the emitter-coupled transistor pairs in the second gating level switches in response to the signal magnitude on the node B against the threshold voltage VT.sub.3. Finally, the FIG. 1 prior art circuit includes a third gating level having a single emitter-coupled transistor pair Q.sub.20 Q.sub.21. The emitter-coupled node of the third gating level pair is connected to the collector of a circuit current source transistor Q.sub.30. The current source transistor Q.sub.30 is connected between the emitter node of the third gating level transistor pair and the circuit ground node.
The prior art circuit of FIG. 1 can provide one or more outputs, each corresponding to a respective combination of the three inputs A, B, and C. For this example, the output Y is taken between the collector of Q.sub.2 and the resistor R.sub.1 in the first gating level of the circuit. This output corresponds to a Boolean expression Y=f(A, B, C). Relatedly, the magnitude of Y assumes one of two levels. The output, Y, is conventionally provided by the FIG. 1 circuit through the emitter follower Q.sub.40. This configuration provides the very desirable feature of resistance transformation over a broad frequency range. In practice, the gating level input nodes A, B, and C receive signals having voltage characteristics similar to the Y output. Typically, the voltage swing for each output is 500 mV; for each gating level, the voltage swing is centered around the VT value for the gating level. Therefore, the resistor R.sub.1 is selected such that the Y output has a swing of Vcc-VBE.sub.Q40 to Vcc-VBE.sub.Q41 -0.5Vdc. The first level gating threshold, VT.sub.2, therefore is Vcc-VBE-0.25Vdc. The second level threshold voltage, VT.sub.3 is a diode voltage drop below VT.sub.2, or Vcc-2VBE-0.25Vdc. Finally, the third gating level threshold voltage VT.sub.4 is Vcc-3VBE-0.25Vdc. It will be appreciated that the input circuits for the second and third gating levels are designed to account for the cumulative base-to-emitter voltage drops which determine the respective gating level threshold voltages. Thus, the emitter follower transistor Q.sub.9a provides, through its base-to-emitter junction, a VBE voltage drop to account for the VBE voltage drop by which the threshold voltage VT.sub.3 exceeds the threshold voltage VT.sub.2. Similarly, Q.sub.19a and Q.sub.19b provide the double VBE drop required to account for the corresponding value in the threshold voltage VT.sub.4. The emitters of the input followers Q.sub.9a and Q.sub.19a Q.sub.19b are connected, through a respective resistor to ground. Thus, the emitter resistor for each input follower sets an average current value which varies positively when the input to the input follower rises and negatively when the level falls.
Increasingly, the application specifications for circuits such as are represented by FIG. 1 call for operation in extremely hostile environments. For example, space and military applications commonly require circuit operations over a temperature range of -55.degree. C. to 125.degree. C. Further, the systems incorporating these circuits are specified to operate with voltage sources which vary in operation by + or -10%. For example, space and military operational requirements frequently specify that the circuit voltage represented by Vcc will vary from 4.5VDC to 5.5VDC.
These operational ranges impose conditions on the circuit of FIG. 1 which cause its operational characteristics to vary undesirably. The principal cause of such undesirable variation is the prevailing design philosophy which seeks to stabilize certain circuit parameters by limiting the variation range of the circuit voltage Vcc. This voltage is regulated in an attempt to stabilize the magnitude of the circuit current generated by the transistor Q.sub.30. The thought is that stabilization of Vcc will result in stabilization of the collector voltage of the transistor Q.sub.30, that is, V.sub.C (Q.sub.30). Stabilization of the circuit current will result in the input and output characteristics of the FIG. 1 circuit remaining relatively invariant. As is known, the input and output impedance of an emitter follower are determined by the value of emitter current drawn by the follower. Varying the level of emitter follower current will vary the output resistance and capacitance and the input resistance and capacitance of the follower. Since the interconnections between multi-level gating circuits such as that illustrated in FIG. 1 are made through emitter followers such as the output follower Q.sub.40 and the input follower Q.sub.9a, it will be appreciated that variation of the currents through those followers will vary the time response of a circuit comprising concatenations of the FIG. 1 circuit. Thus, if, for example, the circuit current generated by the transistor Q.sub.30 varies, the output characteristics of the output follower Q.sub.40 will vary as a result. Similarly, if the current provided by the transistor Q.sub.30 varies, the input characteristics of the input follower Q.sub.9a will vary. As is known, over the specified space and military operational ranges, the propagation delay through the circuit of FIG. 1 does vary because of changes in the currents flowing through the gating levels and through the input and output followers of the circuit.
The reason for the variation in input and output characteristics of the FIG. 1 circuit is found in the current generator Q.sub.30 the output follower Q.sub.40.
The reason for this variation can be understood with reference to the circuit current source transistor Q.sub.30. The transistor Q.sub.30 consists of a collector 10, an emitter 11, a base 12, and an emitter node 13 which is connected through a resistor 14 to ground. As is known, the magnitude of the circuit current which flows through the three levels of gating is established by the voltage drop across the resistor 14. If this voltage varies, the voltage drop across, and therefore, the current through the resistor 14, will vary. In the prior art circuit, V.sub.CS is invariant over the temperature range. However, as is known, the base-to-emitter drop between the base 12 and emitter 11 of the transistor Q.sub.30 does exhibit a temperature sensitivity which is usually expressed in the form of a negative temperature dependence curve. In this regard, the base-to-emitter voltage increases as the ambient temperature decreases. In the silicon technology currently utilized in the production of IC circuits, the temperature dependence has a value of approximately 1.5 mV/.degree.C. Customarily, the variation is calculated as a deviation from the base-to-emitter voltage VBE measured at 25.degree. C. In current silicon IC technology, VBE is characteristically 0.8Vdc. Manifestly then, as the ambient temperature of the transistor Q.sub.30 varies, the base-to-emitter voltage will vary. The voltage magnitude at the node 13 is V.sub.CS -VBE.sub.(Q30) ; therefore, as temperature varies, the node voltage varies, thereby altering the value of the circuit current.
Assuming now that the ambient temperature of the FIG. 1 circuit varies negatively, and that V.sub.CS remains stable, one can see that the voltage at the node 13 will drop as a result of an increase in the base-to-emitter voltage of the transistor Q.sub.30, thereby reducing the magnitude of the circuit current. With the decrease in the circuit current, the voltage drop across R.sub.1 will decrease, thereby reducing the voltage swing in Y. Reduction in the voltage swing of Y will reduce the noise margin of the output signal, thereby increasing the susceptibility of the following stage to noise. Further, variation of the output current flowing through the follower Q.sub.40 varies the output resistance of the follower Q.sub.40, thereby varying the response time of the FIG. 1 circuit and its following stage. Finally, variation of the currents flowing in the input followers Q.sub.9a and Q.sub.19a Q.sub.19b alters the input characteristics at the B and C terminals.
The principal reason for stabilizing the current generator bias voltage V.sub.CS is to avoid the possibility of saturating the circuit current source transistor Q.sub.30. The concern is that providing a negative temperature characteristic to V.sub.CS will raise the level of this voltage in response to a reduction in ambient temperature to a point where the base-to-collector diode of the transistor Q.sub.30 becomes forward biased, thereby saturating the transistor Q.sub.30. To date, this concern over saturation has resulted in the stabilization of V.sub.CS and the attempt to stabilize input, output, and circuit currents by regulation of Vcc. Additionally, the operating ranges of the FIG. 1 circuit are derated in order to avoid saturation of Q.sub.30. Since the principal threat of saturation arises when the circuit voltage and temperature are simultaneously at the low ends of these ranges, the low ends are raised. For example, the operational specifications for one available multilevel gating circuit are V.sub.CS =1.23 V varying and Vcc=4.75 V. Without such derating of Vcc, the prior art circuit continues to exhibit changes in propagation delay and noise margin. With derating of Vcc, the circuit is not able to meet the operational voltage and temperature ranges stipulated for military and scientific applications.